Friday, April 24, 2026

Synopsys Partners with TSMC on Next-Gen AI Systems with Silicon Proven IP

Synopsys, Inc. has declared a deepening of its design support suite for the very TSMC’s leading process and packaging technologies. The partnership is about providing verified silicon IPs, EDA workflows driven by AI, and top-tier system solutions tailored for TSMC’s 3nm and 2nm sets along with the innovative A16 (with Super Power Rail) and A14 process nodes.

Through the integration of smart digital, analog, and verification processes with advanced 3D multi-die design along with optical-to-electrical conversion, Synopsys is enabling designers to enhance multiphysics output and speed up development cycles for the most complex AI and HPC computing architectures.

“TSMC’s most advanced process and packaging technologies are opening new frontiers for performance, bandwidth, and energy efficiency in AI and autonomous systems,” said Michael Buehler-Garcia, Senior Vice President at Synopsys. “Through our deep collaboration, Synopsys is delivering AI-driven design flows, advanced multiphysics signoff, and a comprehensive portfolio of proven interface and foundation IP that help customers accelerate innovation and achieve outstanding quality of results.”

Driving Innovation through the Open Innovation Platform

This enhanced collaboration between the two companies is critical for meeting the skyrocketing demands of the AI era, where performance, integration, and energy efficiency are the primary drivers of competitive advantage.

Also Read: AODocs Announces Partnership with Microsoft on AI Enterprise Document Control and Management

“Our collaboration with Open Innovation Platform® (OIP) ecosystem partners like Synopsys continues to expand across TSMC’s advanced nodes and 3DFabric® technologies to meet the rapidly growing demands of AI and high-performance computing,” said Aveek Sarkar, Director of the Ecosystem and Alliance Management Division at TSMC. “By combining Synopsys’ certified EDA solutions and IP portfolio with our latest process and packaging innovations, we are enabling customers to push the boundaries of performance, integration, and energy efficiency-driving leadership silicon for the next-generation of AI systems.”

Comprehensive 3D Multi-Die Analysis and Signoff

As multi-die designs increase in scale, the need for integrated multiphysics analysis becomes vital. Synopsys and TSMC have enhanced support for 3DFabric® technologies, including TSMC-SoIC® and CoWoS® for 5.5x reticle interposer sizes.

Unified Workflow: The 3DIC Compiler platform enables productivity gains through automation from early exploration through final signoff.

Multiphysics Integration: By integrating RedHawk-SC™, RedHawk-SC Electrothermal™, and Ansys HFSS™ software, the platform delivers robust analysis for thermal, power, and high-speed signal integrity.

Advanced Coverage: Enablement extends from A16™ to A14, with PathFinder-SC™ providing multi-die electrostatic discharge (ESD) signoff coverage down to the N2 node.

Photonic Enablement: New capabilities for COUPE support the design of co-packaged optical solutions, utilizing Ansys Zemax OpticStudio® and Ansys Lumerical™ for photonic device simulation.

Accelerating Productivity with AI-Assisted EDA

Synopsys is pushing the boundaries of design efficiency by integrating “agentic” run assistance into the Fusion Compiler™ on TSMC’s A14 process. By leveraging the NanoFlex Pro architecture, the system proactively identifies timing improvement opportunities. Furthermore, ongoing enablement of AI-assisted physical verification in Synopsys IC Validator™ is set to accelerate Design Rule Check (DRC) resolution, ensuring faster tapeout quality.

Leadership in High-Performance IP

Synopsys continues to expand its IP portfolio to address the bandwidth-hungry requirements of data center and edge AI. Recent innovations include:

224G IP Solution: Supporting co-packaged optical Ethernet and UALink to fulfill the bandwidth requirements for future generations.

Silicon Achievements: Making first-silicon achievements in N5, N3P, and N2P nodes with a diverse set of protocols like PCIe 7.0, HBM4, DDR5 MRDIMM Gen2, LPDDR6, and UCIe 64G.

Such innovations cement Synopsys’ position as a building block provider for future silicon, assisting their customers in scaling up their capabilities amid changing market dynamics.

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