Semiconductor companies have reached the stage where the physics laws governing their processes face resistance in meeting the growing needs of the current wave of development associated with Artificial Intelligence (AI). As there is a rising requirement for higher compute density for training large-scale LLMs and using Physical AI systems (including robotics and self-driving cars), monolithic chips are approaching their physical capacity limits. Thus, further progress implies a shift towards finer processes and multi-die technologies.
In response to this crucial challenge in microelectronics, Cadence Design Systems, Inc., and Samsung Foundry recently revealed an unprecedented long-term strategic cooperation. Specifically, Samsung is introducing a fully-certified and sign-off ready EDA and SDA platform designed for its second-generation 2nm technology and sophisticated 3D-IC packaging.
With the help of the innovative “Agentic AI” design workflows from Cadence and Samsung multi-die innovations, the giants have created a design guide for the upcoming generations of data center chips and edge computing solutions.
Co-Optimizing Silicon and Software for the AI Age
The core of the announcement, highlighted at the Samsung Advanced Foundry Ecosystem (SAFE™) 2026 event, is the comprehensive certification of Cadence’s digital, custom analog, and 3D-IC software suites on Samsung’s refined 2nm node. This integration bridges the gap between software design simulation and actual hardware manufacturing.
Key pillars of the 2nm and 3D-IC platform include:
Agentic AI Design Workflows: The platform embeds Cadence Cerebrus™ Intelligent Chip Explorer and multi-agent AI design tools. These autonomous software agents collaborate across the design pipeline-with one agent predicting performance, power, and area (PPA) while another automatically optimizes layout routing-slashing design turnaround time (TAT) by up to 50%.
Advanced 3D Cube-H Architecture: The certified flow provides an opportunity for overall design for Samsung’s 3D Cube-H architecture, using Hybrid Copper Bonding (HCB). The packaging technology makes it possible to stack chiplets vertically with nearly zero interconnect space, facilitating high-bandwidth communication between separate silicon dies.
Silicon Interposer Auto-Routing: Available on the Cadence Integrity™ 3D-IC Platform, this feature automates the extremely challenging routing of millions of pins through a common silicon interposer, maintaining data integrity while reducing any kind of signal loss.
Memory and Interface IP Portfolio: The partnership brings a new range of Memory and Interface IP, optimized specifically for NVIDIA’s NVLink-C2C (chip-to-chip) high bandwidth interconnects and CUDA-X GPU-accelerated computation engineering libraries.
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Industry leaders are already embracing the solution. The graphic computing industry leader, NVIDIA, is taking advantage of the co-optimized flows to design next-generation data center architectures, while edge-silicon innovator, Ambarella, is adopting the solution to design low-power 2nm PCIe 5.0 SoC.
Impact on the Semiconductors & Electronics Sector
The collaboration between Cadence and Samsung Foundry represents a vital milestone for the broader Semiconductors & Electronics ecosystem:
1. Accelerating the Transition to the Chiplet Era
As the cost of manufacturing large, monolithic dies at the 2nm node rises, the industry is shifting toward Heterogeneous Integration. Instead of forcing an entire system onto a single piece of silicon, designers can split an architecture into specialized “chiplets” (e.g., separating AI accelerators, analog I/O, and memory) and fuse them back together using 3D-IC packaging. Cadence and Samsung are standardizing this methodology, making multi-die assembly accessible to mid-market chip design firms.
2. Hardware-Software Co-Design via GPU Acceleration
Advanced node simulation is computationally intensive. By optimizing Cadence’s EDA engines to run directly on NVIDIA’s GPU-accelerated computing infrastructure, the time required to run complex electromigration, thermal, and IR-drop signoff analysis is reduced from days to hours. This creates a continuous feedback loop between layout design and physical simulation, moving the industry closer to a “shift-left” engineering framework.
3. Mitigating the Glitch Power and Thermal Bottleneck
At sub-3nm geometries, “glitch power”-unintended electrical transitions that waste power before a circuit stabilizes-can account for a significant portion of a chip’s total power consumption. Cadence’s Genus™ Synthesis Solution introduces specialized glitch power optimization directly into Samsung’s 2nm place-and-route flows, allowing edge-devices and mobile SoCs to maximize performance-per-watt metrics.
Overall Effects on Businesses Operating in the Industry
For fabless chip design firms, electronic component suppliers, and system integrators, this 2nm deployment reshapes operational realities:
Reducing Risk of Advanced Node Entry: The development of chip designs at 2nm is always fraught with significant business risk because of complex layouts and possible DRC issues. Using a pre-validated and ready-to-go platform provides engineering teams peace of mind in developing their own silicon chips without the risk of massive layout failure.
Accelerating Product Development Timelines: Using autonomous and agent AI for tasks like transistor sizing and layout optimization can enable engineers to concentrate on designing unique architectures for their AI chips. This way, the design turnaround can be reduced by months, allowing businesses to launch advanced products sooner than their competitors using legacy technologies.
Diversifying Foundry Approaches: With Samsung Foundry creating a reliable 2nm ecosystem in addition to its current partnership with Cadence, it gains an upper hand as another suitable foundry for making advanced node chips. This dual foundry arrangement will increase strategic options for tech companies and reduce dependency on certain geographic locations or geopolitical considerations.
Conclusion
This new level of partnership between Cadence and Samsung Foundry is an unmistakable recognition that the future of cutting-edge electronic devices demands a holistic approach to the design and manufacturing processes of silicon. By developing an automated platform infused with agentic AI in 2nm and 3D IC designs, these companies will create the necessary framework to support the growth of the global economy powered by AI. It is clear from the perspective of the semiconductor industry that only by verticalization, automation, and collaboration can one solve the problem of the limitations of the traditional silicon.
