Cadence announced it is furthering its longstanding collaboration with TSMC to accelerate time to silicon for 3D-IC and advanced-node technologies through certified design flows, silicon-proven IP and ongoing technology collaboration. As a leading provider of IP for TSMC N2P, N5 and N3 process nodes, Cadence continues to deliver cutting-edge AI-driven design solutions to the TSMC ecosystem for multiple horizontal applications from chiplets and SoCs to advanced packaging and 3D-ICs. The deep collaboration encompasses certified tools and flows for TSMC’s N2P and A16™ technologies, paves the way for TSMC’s A14 and further unlocks 3D-IC possibilities by extending support for TSMC 3DFabric® design and packaging. In addition, Cadence and TSMC are extending tool certification for newly announced TSMC N3C technology based on available N3P design solutions.
N2P and A16 AI Silicon Design
Cadence is driving innovation in AI chip design with certified tools and optimized IP for TSMC’s advanced N2P and A16™ process technologies. Reinforcing its memory IP leadership, Cadence offers TSMC9000 pre-silicon-certified DDR5 12.8G IP for N2P. Cadence® digital, custom/analog design and thermal analysis solutions are certified for TSMC N2P and A16 technologies. Combined with continued collaboration on AI-driven digital design solutions for N2P, including leveraging large language models (LLMs), these advancements play an important role in improving digital design flows for future process nodes.
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Leading-Edge Automotive Solutions
ADAS, autonomous driving and software-defined vehicles are driving the need for leading-edge silicon for next-generation applications, and Cadence is accelerating this evolution with certified IP for TSMC’s N5A and N3A processes. Cadence’s high-performance design IP portfolio-featuring LPDDR5X-9600, PCI Express® (PCIe®) 5.0, CXL 2.0, 25G-KR and 10G multi-protocol SerDes-is specifically optimized for automotive use.
Expanding and Elevating 3DFabric Solution
Cadence provides the only complete chiplet design, packaging and system analysis solution for TSMC 3DFabric®. Cadence is expanding its design IP portfolio to meet the demands of the AI training market, delivering TSMC 9000-certified IP for 3D-IC design, including HBM3E 9.6G in N5/N4P and pre-silicon HBM3E 10.4G in N3P, alongside Universal Chiplet Express™ (UCIe™) 16G N3P solutions. In addition, Cadence’s HBM4 test chip is pre-silicon-ready for tapeout, which is paving the way for CoWoS-L.
The Cadence Integrity™ 3D-IC Platform now features enhanced support for improved quality of results (QoR) and 3DIC full flow QC with reference flows for 3Dblox, while enabling global resource optimization, chip-package co-design and advanced multiphysics convergence analysis across static timing, power-IR and thermal. New support includes feedthrough creation for multi-chiplet designs and AI-powered tools for end-to-end 3D-IC planning, partitioning and optimization.
SOURCE: Businesswire