Socionext Inc.’s recent advances in artificial intelligence, the company is moving towards leveraging agentic AI for large-scale SoCs that use advanced process nodes. With already successful AI incorporation into the front-end of the design flow, the company is teaming up with EDA leader Cadence Design Systems, Inc. to implement agentic AI processes within complex semiconductor design flows.
As designs of sub-3nm chip architecture become increasingly complex, semiconductor engineers experience greater difficulties with routing density, thermal design, and physical layout optimization. In order to solve these operational problems, Socionext incorporates agentic and generative AI tools from Cadence into its physical design flow, beginning with an innovative large-scale 3nm SoC design.
Agentic AI Implementation in Front-End and Physical Semiconductor Design Engineering
Agentic AI was initially used by Socionext in front-end design flow to optimize functional verification, root cause analysis, and capture of organizational knowledge. Through the incorporation of agentic AI into physical design, the company is looking to integrate front-end logic design with back-end physical design.
Such an integration of AI would enable automatic design iterations and verification, allowing semiconductor engineers to focus on innovations.
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Institutionalizing Engineering Knowledge into Automated Physical Design Workflows
A core element of Socionext’s physical design strategy is the systematic capture and reuse of proprietary engineering methodologies. Utilizing Retrieval-Augmented Generation (RAG), Model Context Protocol (MCP) support, and domain-specific AI skills, Socionext connects internal design databases directly with agentic design tools.
This knowledge-grounded framework operationalizes proprietary engineering expertise across key back-end design phases:
Automated Floorplanning: Utilizing historical layout data and constraint rules to optimize macro placement and reduce wire length.
Customized Timing Analysis Checks: Utilizing customized scripts and rules to expedite signoff verification and overcome static timing analysis limitations.
Checklist and Verification Automation: Creating consistent layout verification rules for multiple engineering sites to guarantee DRC compliance before tape-out.
“As semiconductor design complexity grows, engineering organizations need better ways to capture and reuse expertise across projects and teams,” said Chin-Chi Teng, senior vice president and general manager of the Digital and Signoff Group at Cadence. “Socionext’s implementation demonstrates how the open and extensible InnoStack AI Super Agent enables customers to integrate their own methodologies and proprietary engineering knowledge into AI-assisted design environments. Together, Cadence’s technology and Socionext’s engineering expertise make valuable design knowledge more accessible and actionable across the organization.”
“Socionext has already incorporated AI into front-end design activities and is applying AI-driven design to the physical design of a large-scale 3nm SoC,” said Hisato Yoshida, Presdient and COO of Socionext. “Building on these efforts, we are advancing our AI-driven design capabilities through our collaboration with Cadence and applying the Cadence InnoStack AI Super Agent to SoC development projects. We expect to achieve up to 5X overall productivity gains through Cadence’s agentic AI workflow. By combining our accumulated design knowledge, methodologies, and engineering experience with Cadence technology, we aim to improve design quality and enable engineers to focus on higher-value innovation across the entire SoC development flow.”
Driving Scalable Semiconductor Design Transformation
Beyond immediate speed and efficiency gains, Socionext’s deployment of the Cadence InnoStack AI Super Agent establishes a scalable framework for preserving institutional engineering know-how. By converting proprietary design rules and domain expertise into reusable organizational assets, Socionext ensures consistent design quality and reliability across consecutive chip generations.
