Cadence Design Systems, announced a groundbreaking advancement in pre-silicon power analysis, achieved through its deep collaboration with NVIDIA. By harnessing the capabilities of the Cadence® Palladium® Z3 Enterprise Emulation Platform and the new Cadence Dynamic Power Analysis (DPA) App, the two companies have accomplished what was once thought unattainable – hardware-accelerated dynamic power analysis of billion-gate AI designs across billions of cycles in just hours, with up to 97% accuracy.
This milestone marks a major leap for semiconductor and system developers building solutions for artificial intelligence (AI), machine learning (ML), and GPU-accelerated computing, enabling them to design more energy-efficient systems and bring products to market faster.
Addressing the Power Analysis Bottleneck
As AI and high-performance computing architectures grow exponentially in complexity, engineers face unprecedented challenges in predicting power consumption under realistic workloads. Traditional power analysis methods typically scale to only hundreds of thousands of cycles – a limitation that forces design teams into long, impractical analysis timelines.
Through hardware-assisted acceleration and parallel processing innovations, Cadence and NVIDIA have broken through this barrier, delivering billion-cycle precision at early design stages – a capability that allows for energy optimization before tapeout and without slowing project schedules.
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“Cadence and NVIDIA are building on our long history of introducing transformative technologies developed through deep collaboration,” said Dhiraj Goswami, corporate vice president and general manager at Cadence. “This project redefined boundaries, processing billions of cycles in as few as two to three hours. This empowers customers to confidently meet aggressive performance and power targets and accelerate their time to silicon.”
“As the era of agentic AI and next-generation AI infrastructure rapidly evolves, engineers need sophisticated tools to design more energy-efficient solutions,” said Narendra Konda, vice president, Hardware Engineering at NVIDIA. “By combining NVIDIA’s accelerated computing expertise with Cadence’s EDA leadership, we’re advancing hardware-accelerated power profiling to enable more precise efficiency in accelerated computing platforms.”
From Early Modeling to Optimized Silicon
Using the Palladium Z3 Platform with the DPA App, engineers can now simulate and verify power consumption under real-world workloads long before fabrication. This means:
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Functionality, performance, and power can be evaluated in parallel.
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Over- and under-design risks can be minimized.
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Energy efficiency gains can be realized without delaying schedules.
For AI, ML, and GPU-driven applications, where energy per computation is a defining competitive metric, this early modeling capability enables optimal design trade-offs. Integrated into Cadence’s broader analysis and implementation suite, Palladium DPA supports power estimation, reduction, and signoff across the entire chip development cycle – resulting in more efficient silicon and systems from the ground up.