Avicena is unveiling a modular interconnect platform with multi-Tbps/mm shoreline density based on its LightBundle™ microLED technology, supporting a wide range of die-to-die interfaces.
Avicena, headquartered in Sunnyvale, CA, is announcing its new scalable LightBundle chiplet interconnect at OFC 2024 in San Diego, CA. The chiplet interconnect extends ultra-high density die-to-die (D2D) connections up to 10m at multi-Tbps/mm shoreline bandwidth density and class leading sub-pJ/bit energy efficiency. Based on Avicena’s LightBundle platform which supports unprecedented shoreline density and energy efficiency, it unlocks increased performance from HPC and AI cluster architectures.
Scalable LightBundle Chiplet Platform for D2D Interconnects
Artificial intelligence (AI) is driving an unprecedented surge in demand for compute and memory performance, driven by applications like ChatGPT based on large language models (LLMs). This requires ever higher density, lower power, longer interconnects between processors and different types of memory modules.
High Bandwidth Memory (HBM) modules must be located within a few millimeters of a Graphics Processing Unit (GPU), limiting accessible memory bandwidth and capacity based on GPU shoreline. The LightBundle chiplet interconnect extends HBM and other ultra-high performance D2D connections up to 10m while dissipating < 1pJ/bit for the optical interconnect and supporting multi-Tbps/mm beachfront density. This enables GPUs and other high-performance ICs to greatly increase their total IO bandwidth, accessing vastly more HBM and relieving inter-processor bottlenecks. The LightBundle chiplet is compatible with standard multichip packaging and supports a wide range of D2D interfaces including standard and advanced versions of UCIe and BOW. Avicena is working with selected partners on different implementations. Initial prototypes will be available in the second half of 2025.
“At Avicena, we are excited to announce our ultra-low power scalable chiplet interconnect based on our LightBundle platform,” says Bardia Pezeshki, Founder and CEO of Avicena. “The first D2D implementation will be an 8Tbps UCIe advanced interconnect with a total chiplet footprint of 4mm x 7mm, beachfront density of 2Tbps/mm and power consumption of < 12W.”
“As generative AI continues to evolve, the role of high bandwidth-density, low-power and low latency interconnects between GPUs and HBM modules cannot be overstated”, says Vlad Kozlov, Founder & CEO of LightCounting. “Avicena’s microLED based interconnect technology has the potential to deliver a paradigm shift in die-to-die interconnects.”
SOURCE: BusinessWire