The semiconductor manufacturing industry worldwide has reached an optical and physical barrier. During the past two decades, the advanced semiconductor manufacturing process used a reticle of a standardized size, which is the standard 6-inch-by-6-inch photomask. Photomasks are used to produce a circuit pattern onto silicon wafers through the projection of extreme ultraviolet (EUV) light.
However, with the introduction of semiconductor manufacturing below 2 nanometers using High-Numerical Aperture Extreme Ultraviolet (High-NA EUV) lithography systems, there has been a serious physical barrier to the traditional size of photomasks.
High-NA EUV lithography utilizes anamorphic optics that magnify light differently along horizontal and vertical axes (8x reduction vertically, 4x reduction horizontally). When using standard 6-inch photomasks, this optical reduction cuts the exposure field size in half compared to conventional EUV. To print large artificial intelligence accelerators, server CPUs, and graphics processors, chipmakers were forced to split single die designs across two separate photomasks using complex “stitching” techniques.
Die stitching introduces severe manufacturing friction, including alignment errors, lower wafer yield, increased mask count, and longer exposure times per wafer.
Breaking free from this bottleneck, TSMC (semiconductor foundry company) and ASML (lithography company) have revealed the development of Large Format Photomasks tailor-made for High-NA EUV lithography.
Moving on from traditional six inches, the standard will bring full-field exposure back into the picture, allowing chipmakers to produce extremely large artificial intelligence processors without the need for die stitching.
Bringing Foundry Scale and Lithographic Optics Together
The partnership sets out to create a roadmap that standardizes large-format masks, pellicles, AMHS, and lithography scanners throughout the semiconductor value chain. Through collaboration, TSMC and ASML seek to ensure that mask makers, optical suppliers, and equipment suppliers work together towards the development of consistent specifications before production.
Key technical and operational pillars of the transition include:
Elimination of Die Stitching Overhead: Restores standard full-field exposure dimensions, allowing hyperscale AI chips to be printed on a single exposure pass.
Maximizing Scanner Throughput: Eliminates double-exposure reticle swaps per die, boosting ASML High-NA EUV wafer-per-hour throughput and lowering lithography cost per wafer.
Standardizing the Infrastructure Ecosystem: Works alongside mask blank suppliers, pellicle manufacturers, and inspection toolmakers to establish certified large-format packaging and transport pods.
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Seamless Integration into TSMC Sub-2nm Nodes: Integrates large-format photomask capabilities directly into TSMC’s sub-2nm fabrication pipelines, ensuring commercial deployment for hyperscale AI clients.
“As AI workloads demand larger silicon footprints and sub-2nm transistor density, lithography innovation must extend to the entire photomask infrastructure,” stated Dr. Y.J. Mii, Executive Vice President at TSMC.
Impact on the Semiconductor Industry
The joint announcement by TSMC and ASML marks a fundamental structural shift across the broader Semiconductors landscape:
1. Ending a 20-Year Reticle Size Plateau
Historically, the semiconductor industry maintained the 6-inch photomask standard across multiple lithography node transitions. Breaking this two-decade reticle plateau formalizes the transition toward Multi-Format Lithography Systems. Mask shops and foundries must now upgrade cleanroom automation, inspection systems, and deposition equipment to handle larger glass substrates.
2. Extending Moore’s Law for Hyperscale AI Processors
Modern artificial intelligence accelerators contain tens of billions of transistors and approach physical reticle size limits. Eliminating die stitching bottlenecks enables chip designers to create larger monolithic dies or mega-chiplet assemblies without facing optical stitching defects, extending the economic and physical scaling trajectory of Moore’s Law.
Overall Effects on Businesses Operating in the Sector
The ASML-TSMC standard provides operational benefits for the following companies:
Faster Time to Market: Fabless chip designers will no longer need to rework physical design layouts to account for stitching lines when taping out monolithic sub-2nm AI processors.
New Revenue Cycles for Capital Equipment Suppliers: The equipment suppliers will gain new revenue cycles due to upgrades of mask inspection, cleaning, and etch equipment at foundries.
Lowering Defect Density and Yield Loss: Printing complex circuits under a single optical pass reduces alignment errors and edge defects, increasing prime wafer yields for foundry customers.
Conclusion
TSMC and ASML’s joint initiative to transition the semiconductor industry to large-format photomasks represents a vital milestone in the evolution of High-NA EUV lithography. By overcoming reticle field size constraints, these two industry leaders are providing a practical blueprint for sub-2nm chip manufacturing. For the global semiconductor industry, this announcement confirms that sustaining the pace of artificial intelligence innovation requires bold, systemic hardware standardization across the entire manufacturing ecosystem.
