SK hynix Inc. (or “the company”, www.skhynix.com) announced that it has developed the industry’s highest 238-layer NAND Flash product.
The company has recently shipped samples of the 238-layer 512Gb triple level cell (TLC)* 4D NAND product to customers with a plan to start mass production in the first half of 2023. “The latest achievement follows development of the 176-layer NAND product in December 2020,” the company stated. “It is notable that the latest 238-layer product is most layered and smallest in area at the same time.”
* Triple Level Cell (TLC): NAND Flash products are categorized into Single Level Cell, Multi Level Cell, Triple Level Cell, Quadruple Level Cell and Penta Level Cell depending on the number of information (unit: bit) contained in a single cell. That a cell contains more information means more data can be stored within the same extent of area.
The company unveiled development of the latest product at the Flash Memory Summit 2022* in Santa Clara. “SK hynix secured global top-tier competitiveness in perspective of cost, performance and quality by introducing the 238-layer product based on its 4D NAND technologies,” said Jungdal Choi, Head of NAND Development at SK hynix in his keynote speech during the event. “We will continue innovations to find breakthroughs in technological challenges.”
* Flash Memory Summit (FMS): The world’s biggest conference for NAND Flash industry taking place in Santa Clara every year. During its keynote speech at the event SK hynix made a joint announcement with Solidigm.
Since development of the 96-layer NAND product in 2018, SK hynix has introduced a series of 4D products that outperform existing 3D products. The company has applied charge trap flash* and peri under cell* technologies to make chips with 4D structures. 4D products have a smaller cell area per unit compared with 3D, leading to higher production efficiency.
* Charge Trap Flash (CTF): Unlike floating gate, which stores electric charges in conductors, CTF stores electric charges in insulators, which eliminates interference between cells, improving read and write performance while reducing cell area per unit compared to floating gate technology.