MZ Technologies, the marketing arm of Monozukuri S.p.A., is helping expand Europe’s strategically important semiconductor industries by providing European academic institutions with leading-edge advanced EDA design tools at substantial reduced prices.
By collaborating with Europractice Service MZ will provide GENIO™ integrated silicon/packaging co-design tools to universities and research labs throughout Europe.
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GENIO co-plans the final device (package) and integrated electronic circuits (ICs) in complex 2.5-3D chiplet -based hybrid configurations and was recognized by an international jury of industry experts as a revolutionary EDA co-design tool.
Europractice provides academic institutions with affordable access to state-of-the art semiconductor technology for non-commercial education and research. More than 600 European academic institutions across 44 countries actively use Europractice in their teaching and research.
Monozukuri joins global IC industry icons such as ARM, Cadence, Intel, Siemens, Synopsys, and Xilinx in furthering the development of European semiconductor research and design.
“It’s our responsibility to enhance the viability of the European semiconductor industry. Partnering with Europractice give us the opportunity to train the next-generation IC engineers who’ll move this critical industry to new heights,” said Anna Fontanelli, MZ Technologies‘ CEO and Founder.
“Europractice services enable European academics to more easily adopt new technologies to help them train the next generation of semiconductor engineers,” explained Mark Willoughby, Head of Europractice Design Tools. “We’re delighted that MZ Technologies is joining us in this mission.”
Through Europractice, MZ Technologies is making available GENIO™ 1.6, it most up-to-date software. GENIO™ 1.6 includes Parasitic Estimation and Stack Planning functionality that slash total design time and reduces overall design complexity.
Parasitic Estimation enables early-on system analysis, based on virtual routes, prior to physical implementation. Stack Planning Support automatically identifies the best 3D stack configuration, given physical and electrical constraints. It provides a more efficient chiplet-based 3D-IC system organization and electrical performance, while reducing the physical resources (TSVs) required for vertical interconnect.