Cadence announced the release of its cutting-edge HBM4 12.8Gbps memory IP system, setting a new benchmark for memory bandwidth in SoCs designed for next-generation artificial intelligence (AI) training and high-performance computing (HPC) platforms. The Cadence® HBM4 IP solution is fully compliant with JEDEC’s JESD270-4 specification and delivers twice the bandwidth of previous HBM3E offerings, making it the fastest available HBM4 memory system in the industry.
Now available for customer engagements, the Cadence HBM4 solution includes both PHY and controller IP, delivering 12.8Gbps of peak performance, 20% improved power efficiency per bit, and 50% better area efficiency—all while doubling I/O count to support significantly higher data throughput.
The HBM4 PHY is delivered as a hardened drop-in macro for TSMC’s N3 and N2 process nodes, while the HBM4 controller is offered as a flexible soft RTL macro. This complete memory subsystem enables advanced SoC designs to exceed current DRAM speed limits by 60%, providing designers with generous system margin to accommodate evolving speed targets and ensure future-proofed performance.
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Designed for flexibility and performance, the Cadence HBM4 architecture integrates low-latency capabilities, reliability features like RAS (Reliability, Availability, and Serviceability), and built-in self-test (BIST) tools. These enhancements optimize in-field performance, critical for data center scalability. The solution also supports multiple interposer design options and includes lab software to streamline system-on-chip (SoC) memory subsystem bring-up.
“The proliferation of generative and agentic AI applications and the resulting increase in AI workloads demand higher memory bandwidth for greater AI hardware system efficiency without further draining power. Cadence’s HBM4 solution addresses this insatiable need for memory bandwidth by providing the highest performance available at 12.8Gbps while maintaining area and power efficiency—key concerns for AI factories,” said Boyd Phelps, senior vice president and general manager of the Silicon Solutions Group at Cadence.