Cadence Design Systems, announced significant advancements in chip design automation and IP, underscoring its long-standing collaboration with TSMC to deliver cutting-edge design infrastructure for AI and high-performance computing (HPC) applications. By combining expertise across AI-driven EDA, 3D-IC integration, IP, and photonics, Cadence and TSMC are enabling faster development of the world’s most advanced semiconductors.
The companies have partnered to optimize design infrastructure across multiple advanced TSMC process nodes, including N3, N2, and A16™, leveraging the Cadence® Innovus™ Implementation System, Quantus™ Extraction Solution and Quantus Field Solver, Tempus™ Timing Solution and ECO Option, Pegasus™ Verification System, Liberate™ Characterization Portfolio, Voltus™ IC Power Integrity Solution, Genus™ Synthesis Solution, Virtuoso® Studio, and Spectre® Simulation Platform. Cadence AI-enabled design flows for chip and 3D-IC development are now available for these process nodes, as well as for new features in TSMC 3DFabric™.
Cadence is also collaborating with TSMC on flow development for the A14 process, with the first process design kit (PDK) expected later this year. In addition, several new Cadence IP solutions are now silicon-proven and available for TSMC N3P.
“Cadence and TSMC remain committed to speeding up and improving the design process for advanced silicon for our customers,” said Chin-Chi Teng, senior vice president and general manager of the Digital and Signoff Group at Cadence. “We’re helping designers develop the next generation of AI and HPC by supporting TSMC’s leading technologies with AI features, IP and beyond.”
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“TSMC, together with our Open Innovation Platform® (OIP) partners like Cadence, is addressing some of the most intricate challenges in semiconductor development to drive higher performance and energy efficiency in AI systems,” said Aveek Sarkar, director of the Ecosystem and Alliance Management Division at TSMC. “Our enduring partnership continues to empower our mutual customers to accelerate their journey to silicon while driving the rapid proliferation of AI.”
AI-Driven Chip Design for TSMC Advanced Process Nodes
Cadence and TSMC are delivering AI-enhanced design solutions that allow joint customers to optimize power, performance, and area (PPA) at TSMC N2. With TSMC support, the Cadence JedAI Platform™, Cerebrus® Intelligent Chip Explorer, and Innovus+ AI Assistant are integrated within Cadence’s digital full flow to streamline design productivity.
TSMC has also validated new AI-powered features such as automated design rule check (DRC) violation fixing assistance, enabling faster design closure and improved efficiency for AI chip development.
Accelerating 3D-IC Innovation
Cadence’s 3D-IC solutions provide full support for TSMC’s 3DFabric™ advanced packaging and die-stacking technologies. New features include automation for bump connections, multi-chiplet physical implementation and analysis, and smart alignment marker insertion.
With the integration of Clarity™ 3D Solver and Sigrity™ X Platform powered by Optimality™ Intelligent System Explorer, designers can automate system-level SI/PI analysis and optimization within the 3Dblox™ ecosystem.
For customers adopting TSMC Compact Universal Photonic Engine (TSMC-COUPE™) reference flows, Virtuoso Studio and the Celsius™ Thermal Solver deliver advanced thermal simulation techniques. These productivity enhancements reduce thermal risks while improving the electrical and photonic performance of complex systems.