Arteris, a leading provider of system IP for accelerating semiconductor creation, announced an expansion of its multi-die solution, delivering a foundational technology for rapid chiplet-based innovation.
“In the chiplet era, the need for computational power increasingly exceeds what is available by traditional monolithic die designs,” said K. Charles Janac, president and CEO of Arteris. “Arteris is leading the transition into the chiplet era with standards-based, automated and silicon-proven solutions that enable seamless integration across IP cores, chiplets, and SoCs.”
Moore’s Law, predicting the doubling of transistor count on a chip every two years, is slowing down. As the semiconductor industry accelerates efforts to increase performance and efficiency, especially driven by AI workloads, architectural innovation through multi-die systems has become critical. Arteris’ expanded multi-die solution addresses this shift with a suite of enhanced technologies that are purpose-built for scalable and faster time-to-silicon, high-performance computing, and automotive-grade mission-critical designs.
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Arteris’ offering reduces chiplet and SoC design time, along with the optimization of power, performance, and area bottlenecks by providing key Network-on-Chip (NoC) IP technology for standardized die-to-die communication and automating key SoC creation workflows.
Built for interoperability, the expanded solution supports the Universal Chiplet Interconnect Express (UCIe) specification, various Arm AMBA protocols, PCIe, and integration with leading physical IPs to ensure robust, standards-based ecosystem compatibility. Integration with products from major EDA and foundry partners – Cadence, Synopsys and global fabs – ensures a ready-to-deploy solution for silicon innovators and system companies creating electronics.
SOURCE: GlobeNewswire