Keysight Technologies, along with WIN Semiconductors Corp., the pure-play compound semiconductor foundry, has announced their collaboration in developing an MMIC design flow. This unique design flow is specifically designed to support GaN MMIC design companies in reducing fabrication risk and enabling successful first-pass tapeout.
This design flow combines multi-domain simulation, 3D layout verification, and engineering of the MMIC evaluation board in one software environment. This design flow is especially relevant to a new wave of aerospace and defense companies developing high-frequency GaN MMICs used in 5G base station infrastructure, next-generation Wi-Fi access points, advanced satellite payloads, and military radar systems.
Mitigating Costly Foundry Respins and Ensuring Hardened Performance
In high-frequency semiconductor manufacturing, a failed tapeout often translates to weeks of scheduling delays and immense financial overhead due to unexpected foundry respins. The collaborative workflow counters this challenge by automating the exhaustive matrix of simulation, optimization, and Layout Versus Schematic (LVS) verification steps required for technical sign-off, ensuring that comprehensive electrical and physical analyses are executed prior to foundry submission.
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Furthermore, downstream MMIC procurement cycles heavily depend on hardware validation. Corporate enterprise buyers typically require physical verification on an evaluation board-encompassing the MMIC, its packaging, the host PCB, and RF test connectors-before finalizing high-volume purchase agreements. The unified environment allows engineering teams to design and optimize on-chip and off-chip components concurrently, verifying that the entire system meets operational specifications when evaluated alongside precision electronic test equipment. With the global GaN RF device market projected to reach $2.77 billion by 2031, providing verifiable evaluation board performance is vital for design houses looking to capture market share.
Integrated Simulation Powered by Advanced PDK Architecture
The automated workflow relies heavily on WIN Semiconductors’ latest NP 120P GaN Process Design Kit (PDK), which supplies designers with validated process models and strict manufacturing layout rules. When deployed inside Keysight‘s Advanced Design System (ADS) and RF Circuit Simulation Professional software suites, these foundry-specific models automate verification pipelines to accelerate production-ready chip development.
Richard Kuo, Director of Design Service, WIN Semiconductors, said: “We are delighted to collaborate with Keysight to deliver a customized LVS solution within the WIN ADS PDK. By combining Keysight’s ADS expertise with WIN’s robust PDK and advanced process technology, we provided a comprehensive verification solution that streamlined the customer’s design flow and accelerated the time-to-market for advanced RF products with greater confidence and reliability.”
Nilesh Kamdar, General Manager, EDA, Design Engineering Software, Keysight, said: “WIN‘s complete PDK, combined with Keysight’s simulation and verification tools, gives designers a single path from chip design through evaluation board. Design houses can now prove full system performance before fabrication, giving their customers the confidence to commit.”