Microchip Technology has launched its Switchtec™ Gen 6 PCIe® Switches, the industry’s first PCIe Gen 6 switches built on a 3 nm process, designed to deliver high-density AI system connectivity with lower power consumption and support for up to 160 lanes. Addressing bandwidth bottlenecks common in previous PCIe generations, these switches leverage PCIe 6.0’s doubled bandwidth of 64 GT/s per lane to enable high-speed communication between CPUs, GPUs, SoCs, AI accelerators, and storage devices, ensuring optimal utilization of compute resources. “Rapid innovation in the AI era is prompting data center architectures to move away from traditional designs and shift to a model where components are organized as a pool of shared resources,” said Brian McCarson, VP of Microchip’s data center solutions business unit.
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Switchtec Gen 6 incorporates advanced security features, including a hardware root of trust and secure boot with post-quantum safe CNSA 2.0 cryptography, and supports NTB, multicast, hot- and surprise-plug controllers, bifurcation, and multiple I/O interfaces. Efficiency improvements include FLIT-based Forward Error Correction, dynamic resource allocation, and low-latency, high-throughput design optimized for small AI workloads. Development and diagnostics are supported via Microchip’s ChipLink tools and PM61160-KIT evaluation kit, enabling flexible configuration, monitoring, and deployment across next-generation AI and cloud infrastructures.