XConn Technologies, the innovation leader in next-generation interconnect technology for the future of high-performance computing and AI applications, unveiled its Apollo 2 hybrid switch that integrates both Compute Express Link™ (CXL™) 3.1 and Peripheral Component Interconnect Express® (PCIe®) Gen 6.2 interconnect technology on a single high-density chip. Designed to support configurations ranging from 64 to 260 lanes, Apollo 2 sets a new benchmark in flexibility and performance for next-generation computing environments.
Apollo 2 is engineered to meet the demanding needs of AI, machine learning, and high-performance computing (HPC) applications, offering a breakthrough in interconnect technology with its support for the latest standards for both CXL and PCIe protocols. This hybrid approach ensures optimal compatibility and memory performance enhancements across various computing platforms.
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“Building on the success of our Apollo 1 switch, the Apollo 2 switch represents a significant advancement in our technology roadmap,” said Gerry Fan, CEO of XConn Technologies. “This switch not only meets the latest standards of CXL and PCIe but also provides unprecedented density and scalability, which are crucial for the evolving demands of modern data centers and computing architectures.”
Industry leaders are recognizing the Apollo 2 for its innovative design and substantial contributions to the field of computational technology.
“The rapid evolution of AI and high-performance computing applications is driving the need for proven interconnect solutions for keystone companies like XConn,” said Neeraj Paliwal, Senior Vice President of IP Product Management at Synopsys. “XConn’s Apollo 2 switch demonstrates the advantages of integrating Synopsys’ silicon-proven IP to meet the latest CXL 3.x and PCIe 6.x requirements. By leveraging Synopsys’ best-in-class and standards-based PCIe and CXL IP solutions, XConn is minimizing integration risk while optimizing performance, power efficiency, and interoperability, which are key factors in accelerating next-generation computing architectures.”
SOURCE: PRWeb