EV Group, a leading provider of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, introduced NanoCleave™, a revolutionary layer release technology for silicon that enables ultra-thin layer stacking for front-end processing, including advanced logic, memory and power device formation, as well as semiconductor advanced packaging. NanoCleave is a fully front-end-compatible layer release technology that features an infrared (IR) laser that can pass through silicon, which is transparent to the IR laser wavelength. Coupled with the use of specially formulated inorganic layers, this technology enables an IR laser-initiated release of any ultra-thin film or layer from silicon carriers with nanometer precision.
As a result, NanoCleave enables silicon wafer carriers in advanced packaging processes such as Fan-out Wafer-level Packaging (FoWLP) using mold and reconstituted wafers as well as interposers for 3D Stacked ICs (3D SIC). At the same time, its compatibility with high-temperature processes enables completely novel process flows for 3D IC and 3D sequential integration applications – enabling hybrid and fusion bonding even of ultra-thin layers on silicon carriers, thereby revolutionizing 3D and heterogeneous integration as well as material transfer in next-generation scaled transistor designs.
Company executives will be available to discuss this IR laser transfer technology breakthrough at SEMICON Taiwan, taking place at the Taipei Nangang Exhibition Center Hall 1 (TaiNEX 1) in Taipei, Taiwan, from September 14-16. Event attendees can visit EVG at Booth #L0316 (4th Floor) to learn more.
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Silicon Carriers Benefit 3D Stacking and Back-end Processing
In 3D integration, carrier technologies for thin-wafer processing are key to enabling higher performance systems with increasing interconnection bandwidth. Glass carriers have become an established method for building up device layers through temporary bonding with organic adhesives, using an ultraviolet (UV) wavelength laser to dissolve the adhesives and release the device layers, which are subsequently permanently bonded onto the final product wafer. However, glass substrates are difficult to process with semiconductor fab equipment that have been designed primarily around silicon, and that require costly upgrades to enable glass wafer processing. In addition, organic adhesives are generally limited to processing temperatures below 300°C, which limits their use to back-end processing.
Enabling silicon carriers with inorganic release layers avoids these temperature and glass carrier compatibility issues. In addition, the nanometer precision of IR laser-initiated cleaving opens up the possibility of processing extremely thin device wafers without changing processes of record. Subsequent stacking of such thin device layers enables higher bandwidth interconnects and opens up new opportunities to design and segment dies for next-generation high-performance systems.
Next-generation Transistor Nodes Demand Novel Layer-transfer Processes
At the same time, transistor roadmaps for the sub-3-nm node are calling for new architectures and design innovations such as buried power rails, backside power delivery networks, complementary field-effect transistors (CFETs) and even 2D atomic channels, all of which will require layer transfer of extremely thin materials. Silicon carriers and inorganic release layers support process cleanliness, material compatibility and high processing temperature requirements for front-end manufacturing flows. However, until now, silicon carriers had to be completely removed using grinding, polishing and etching processes, which results in micron-range variations across the surface of the working device layer, making this method unsuitable for thin-layer stacking at advanced nodes.